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<title>Sample Waveforms for length_fifo.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file length_fifo.vhd </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design length_fifo.vhd.  The design length_fifo.vhd has a depth of 32 words of 12 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
<CENTER><img src=length_fifo_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<CENTER><img src=length_fifo_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
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